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MR27V6466F Datasheet(PDF) 6 Page - OKI electronic componets

Part No. MR27V6466F
Description  4,194,304-Word x 16Bit or 2,097,152-Word x 32-Bit Synchronous One Time PROM
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Maker  OKI [OKI electronic componets]
Homepage  http://www.oki.com
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MR27V6466F Datasheet(HTML) 6 Page - OKI electronic componets

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PEDR27V6466F-01-08
1Semiconductor
MR27V6466F
6/39
FUNCTION COMMAND TABLE FOR SYNCHRONOUS READ
Command Name
Function
Mode Register
Set
Mode Register Set
H
X
L
L
L
L
X
Code
XL
1
Row Active
Row Address Latch
H
X
L
L
H
H
X
RA
X
L
2
Read Word
(x16)
Column Address Latch
Trigger Burst Read
H
X
LH
LH
X
CA
L
L
3
Read Double
Word (x32)
Column Address Latch
Trigger Burst Read
H
X
LH
LH
X
CA
H
L
3
Burst Stop
Burst Stop
H
X
L
H
H
L
X
X
X
L
4
Precharge
Burst Stop
H
X
L
L
H
L
X
X
X
L
4
Entry
H
L
H
XX
XX
XX
L
5
Clock Suspend
(on Read)
Exit
L
H
XX
XX
X
X
X
L
5
Entry
HL
H
X
XX
X
X
X
L
6
Power Down
(on Active
Standby)
Exit
L
H
XX
XX
X
X
X
L
6
Read Output
Output Enable
H
X
X
X
X
X
L
X
X
L
Mask Output
High-Z Output
H
X
X
X
X
X
H
X
X
L
Write on SDRAM
H
X
L
H
L
L
X
X
X
L
Illegal on SDRAM
H
H
L
L
L
H
X
X
X
L
HXH
X
X
X
X
X
XL
No Operation
HX
L
H
H
H
X
X
XL
( H = Logical high, L = Logical low, X = Don't Care, L of STO includes pin open due to internal pull down resistor)
(CKE
N expresses the logical level at the simultaneous cycle with a command. )
Notes:
1.
Refer to "Mode Register Field Table" for Address Codes, and Mode Transition Chart for operational state.
After power on, any command can be sampled at any cycle in Active Standby state. After "Mode Register
Set" command is sampled, no new command can be accepted for 3 CLK cycles. The
CS input must be
kept high for the 3 CLK cycles to prevent unexpected sampling of a command.
2.
The "Row Active" command is effective till new "Row Active" command is implemented.
3.
The
WORD input is sampled simultaneously with "Read" command to select data width. A Double Word
Burst (x32) or a Word Burst (x16) is selected by the
WORD input for each "Read" command. On
condition of constant voltage level on
WORD pin, the organization is fixed to either x16 or x32. "Read"
command ends it's implementation by itself at the finishing cycle of the burst read.
4.
Since OTP technology uses static sense amplifiers, the "Precharge" command is not required. However,
due to customer request for the similarity of logical input code with SDRAM command, the name of
"Precharge" is adopted. The function of "Precharge" command and "Burst Stop" command is only to stop
the burst read cycles delayed by CAS Latency.
5.
Sampled low level CKE disables CLK buffer to suspend internal clock signals at the next rising edge of
CLK. Sampled high level CKE enables internal clock at the next rising edge of CLK.
Low level CKE sampled in the period from the simultaneous cycle with a "Read" command till the end of
the burst read cycle is distinguished with internal command controller from the low level CKE sampled in
Active Standby state, then power is consumed because of data sensing and burst read operation.
6.
Low level CKE sampled in Active Standby state cuts power dissipation to be in Power Down state. High
level CKE sampled in Power Down state enables internal CKE to be in Active Standby state with
preserved row address.


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