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MSM51V4223C Datasheet(PDF) 1 Page - OKI electronic componets

Part No. MSM51V4223C
Description  262,263-Word × 4-Bit Field Memory
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Maker  OKI [OKI electronic componets]
Homepage  http://www.oki.com
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MSM51V4223C Datasheet(HTML) 1 Page - OKI electronic componets

 
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FEDS51V4223C-03
1Semiconductor
This version: Oct. 2000
Previous version: Feb. 2000
MSM51V4223C
262,263-Word
×××× 4-Bit Field Memory
1/15
GENERAL DESCRIPTION
The OKI MSM51V4223C is a high performance 1-Mbit, 256 K
× 4-bit, Field Memory. It is designed for high-
speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media
systems. It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The
MSM51V4223C is not designed for the other use or high end use in medical systems, professional graphics
systems which require long term picture, and data storage systems and others. The 1-Mbit capacity fits one field of
a conventional NTSC TV screen and cascaded two MSM51V4223Cs make one frame of the screen: more than
two MSM51V4223Cs can be cascaded directly without any delay devices among the MSM51V4223Cs.
(Cascading of MSM51V4223C provides larger storage depth or a longer delay).
Each of the 4-bit planes has separate serial write and read ports that employ independent control clocks to support
asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates
between write and read data streams.
The MSM51V4223C provides high speed FIFO, First-In First-Out, operation without external refreshing: it
refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation,
so that the serial read and/or write control clock can be halted high or low for any duration as long as the power is
on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.
The MSM51V4223C’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set
by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally
controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256
× 4-bit enable high speed first-bit-
access with no clock delay just after the write or read reset timings.
The MSM51V4223C is similar in operation and functionality to OKI 1-Mbit Field Memory MSM51V4221C
besides direct cascade capability. (As for MSM51V4221C operation compatible 2-Mbit Field Memory, OKI has
MSM51V8221A as a sister device of MSM51V8222A).
Additionally, the MSM51V4223C has write mask function or input enable function (IE), and read-data skipping
function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and
between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address
increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to
MSM51V4223C. The input enable (IE) function allows the user to write into selected locations of the memory
only, leaving the rest of the memory contents unchanged. This facilitate data processing to display a “picture in
picture” on a TV screen.


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