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MP7641 Datasheet(PDF) 5 Page - Exar Corporation |
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MP7641 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 24 page MP7641 5 Rev. 2.00 ELECTRICAL CHARACTERISTICS TABLE Description Symbol Min Typ Max Min Max Units Conditions DIGITAL TIMING SPECIFICATIONS2, 4 Input Clock Pulse Width tCH, tCL 40 50 ns Data Setup Time tDS 10 10 ns Data Hold Time tDH 15 15 ns CLK to SDO Propagation Delay tPD 40 50 ns DAC Register Load Pulse Width tLD 100 100 ns Reset Pulse Width tRST 50 60 ns Clock Edge to Load Rising Edge tCKLD1 100 100 ns Clock Edge to Load Falling Edge tCKLD2 00 ns Load Falling Edge to SDO tHZ1 50 60 ns 3-state Enable Load Rising Edge to SDO tHZ2 35 50 ns 3-state Disable Load Falling Edge to CLK Disable tLDCK1 25 40 ns Load Rising Edge to CLK Enable tLDCK2 35 50 ns LD Set-up Time with Respect tLDSU 15 20 ns to CLK 25 °C NOTES 1 Full Scale Range (FSR) is 3V. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See Figures 2 and 3. 5 For reference input pulse: tR = tF > 100 ns. Tmin to Tmax Specifications are subject to change without notice |
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