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ICS889874AKT Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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ICS889874AKT Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 14 page 889874AK www.icst.com/products/hiperclocks.html REV. A MAY 19, 2004 7 Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER PRELIMINARY APPLICATION INFORMATION V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR 3.3V LVPECL OUTPUTS FIGURE 2B. LVPECL OUTPUT TERMINATION FIGURE 2A. LVPECL OUTPUT TERMINATION |
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