1

2003

Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

DSC-4679/3



NOVEMBER 2003

16,384 x 36 x 2

32,768 x 36 x 2

65,536 x 36 x 2

IDT72V3682

IDT72V3692

IDT72V36102

COMMERCIAL TEMPERATURE RANGE

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

FEATURES

IDT72V3682 – 16,384 x 36 x 2

IDT72V3692 – 32,768 x 36 x 2

IDT72V36102 – 65,536 x 36 x 2

(simultaneous reading and writing of data on a single clock edge

is permitted)

tions

functions) or First Word Fall Through timing (using ORA, ORB, IRA

and IRB flag functions)

72V3642/72V3652/72V3662/72V3672

°°°°°C to +85°°°°°C) is available

FUNCTIONAL BLOCK DIAGRAM

Mail 1

Register

Programmable Flag

Offset Registers

RAM

ARRAY

16,384 x 36

32,768 x 36

65,536 x 36

Write

Pointer

Read

Pointer

Status Flag

Logic

Write

Pointer

Read

Pointer

Status Flag

Logic

CLKA

CSA

W/

RA

ENA

MBA

Port-A

Control

Logic

FIFO1,

Mail1

Reset

Logic

RST1

Mail 2

Register

MBF2

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

FIFO2,

Mail2

Reset

Logic

RST2

MBF1

FIFO 1

FIFO 2

16

EFB/ORB

AEB

36

36

FFB/IRB

AFB

FFA/IRA

AFA

EFA/ORA

AEA

4679 drw 01

36

36

Timing

Mode

FWFT

RAM

ARRAY

16,384 x 36

32,768 x 36

65,536 x 36