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Z86017 Datasheet(PDF) 73 Page - Zilog, Inc. |
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Z86017 Datasheet(HTML) 73 Page - Zilog, Inc. |
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73 / 138 page  Z86017/Z16017 PCMCIA Interface Solution Product Specification Programming Internal Registers PS012002-1201 59 EEPROM Register Address: SELECT 18h Name: Window 3 Control Register Type: Write/Read Table 38. Window 3 Control Register: Address 18h Bit Placement Bit Name Description Bit 0 DIS_PAC3 When set to 1, this bit disables Port 3 address control and decoder. Bit 1 EN_PAC3_MEM When this bit is set to 1, Memory mode decoder is enabled. When it is cleared, I/O mode decoder is enabled. Bit 2 EN_PAC3_16+ When this bit is set, data swapping is provided internal to the chip during data reads from the low byte of the ATA bus to the PCMCIA bus high byte, and from the high byte of the PCMCIA bus to the low byte of the ATA bus during data writes. When this bit is cleared, it is high byte to high byte and low byte to low byte. Bit 3 READ_PROTECT This bit allows two cards to be read from the same address. When this bit is set, it prevents the PCMCIA bus from becoming active. Bit 4 EN_PAC3_ADDR_COMP When this bit is set, use address compare logic; when it is cleared, acknowledge all PCMCIA chip selects. Bit 5 EN_PAC3_HCS When this bit is set, HCS1 is used as an external chip select; when it is cleared, HCS0 is used as an external chip select. Bits 7-6 Number of wait states (in Master Clock periods) inserted on the PCMCIA bus. |
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Similar Description - Z86017 |
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