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ZLR16300 Datasheet(PDF) 61 Page - Zilog, Inc. |
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ZLR16300 Datasheet(HTML) 61 Page - Zilog, Inc. |
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61 / 94 page  CrimzonTMZLR16300 Product Specification PS021413-1205 Functional Description 54 Any Port 2 bit defined as an output drives the corresponding input to the default state. This condition allows the remaining inputs to control the AND/OR function. Refer to SMR2 register on page 55 for other recover sources. Stop Mode Recovery Delay Select (D5) This bit, if Low, disables the TPOR delay after Stop Mode Recovery. The default configuration of this bit is 1. If the “fast” wake up is selected, the Stop Mode Recovery source must be kept active for at least 10 TpC. This bit must be set to 1 if using a crystal or resonator clock source. The TPOR delay allows the clock source to stabilize before executing instructions. Stop Mode Recovery Edge Select (D6) A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the CrimzonTM ZLR16300 from Stop Mode. A 0 indicates Low level recovery. The default is 0 on POR. Cold or Warm Start (D7) This bit is read only. It is set to 1 when the device is recovered from Stop Mode. The bit is set to 0 when the device reset is other than Stop Mode Recovery (SMR). Table 18. Stop Mode Recovery Source SMR:432 Operation D4 D3 D2 Description of Action 0 0 0 POR and/or external reset recovery 00 1Reserved 01 0P31 transition 01 1P32 transition 10 0P33 transition 10 1P27 transition 1 1 0 Logical NOR of P20 through P23 1 1 1 Logical NOR of P20 through P27 Note: Note: |
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Similar Description - ZLR16300 |
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