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MAX5331 Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX5331 Datasheet(HTML) 4 Page - Maxim Integrated Products |
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4 / 16 page  12-Bit DACs with 32-Channel Sample-and-Hold Outputs 4 _______________________________________________________________________________________ Note 1: The nominal zero-scale voltage (code = 0) is -4.0535V. The nominal full-scale voltage (code = FFF hex) is +9.0503V. The output voltage is limited by the output range specification, restricting the usable range of DAC codes. The nominal zero- scale voltage can be achieved when VSS < -4.9V, and the nominal full-scale voltage can be achieved when VDD > +11.5V. Note 2: Gain is calculated from measurements: for voltages VDD = 10V and VSS = -4V at codes C00 hex and 4F3 hex for voltages VDD = 11.6V and VSS = -2.9V at codes FFF hex and 253 hex for voltages VDD = 9.25V and VSS = -5.25V at codes D4F hex and 0 hex for voltages VDD = 8.55V and VSS = -2.75V at codes C75 hex and 282 hex Note 3: Steady-state change in any output with an 8V change in an adjacent output. Note 4: Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent updates. Tested with an external sequencer clock frequency of 480kHz. Note 5: External clock mode with the external clock not toggling. Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F3 hex. Note 7: The sequencer runs at fSEQ = fECLK / 4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is limited by acceptable droop and update time after a burst-mode update. Note 8: VDD rise to CS low = 500µs maximum. Note 9: Guaranteed by gain-error test. Note 10: The serial interface is inactive. VIH = VLOGIC, VIL = 0. Note 11: The serial interface is active. VIH = VLOGIC, VIL = 0. ELECTRICAL CHARACTERISTICS (continued) (VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0, RL ≥ 10MΩ, CL = 50pF, CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK-High to CS-High Hold Time tCSH1 0ns DIN to SCLK High Setup Time tDS 15 ns DIN to SCLK High Hold Time tDH 0ns RST-to-CS Low (Note 8) 500 µs POWER SUPPLIES Positive Supply Voltage VDD (Note 9) 8.55 10 11.60 V Negative Supply Voltage VSS (Note 9) -5.25 -4 -2.75 V Supply Difference VDD - VSS (Note 9) 14.5 V Logic Supply Voltage VLOGIC, VLDAC, VLSHA 4.75 5 5.25 V Positive Supply Current IDD 32 42 mA Negative Supply Current ISS -40 -32 mA (Note 10) 1 1.5 Logic Supply Current ILOGIC fSCLK = 20MHz (Note 11) 2 3 mA |
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