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MAX5331 Datasheet(PDF) 3 Page - Maxim Integrated Products

Part No. MAX5331
Description  12-Bit DACs with 32-Channel Sample-and-Hold Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5331 Datasheet(HTML) 3 Page - Maxim Integrated Products

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12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0, RL
≥ 10MΩ, CL = 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Sample-and-Hold Settling
(Note 4)
0.08
%
SCLK Feedthrough
0.5
nVs
fSEQ Feedthrough
0.5
nVs
Hold Step
0.25
1mV
Droop Rate
VOUT_ = 0 (Note 5)
1
300
µV/ms
Output Noise
250
µVRMS
REFERENCE INPUT
Input Resistance
7k
Reference Input Voltage
VREF
2.5
V
GROUND-SENSE INPUT
Input Voltage Range
VGS
-0.5
+0.5
V
Input Bias Current
IGS
-0.5V
≤ VGS ≤ 0.5V
-60
0
µA
GS Gain
(Note 6)
0.998
1
1.002
V/V
DIGITAL-INTERFACE DC CHARACTERISTICS
Input High Voltage
VIH
2.0
V
Input Low Voltage
VIL
0.8
V
Input Current
±1µA
TIMING CHARACTERISTICS (Figure 2)
Sequencer Clock Frequency
fSEQ
Internal oscillator
80
100
120
kHz
External Clock Frequency
fECLK
(Note 7)
480
kHz
SCLK Frequency
fSCLK
20
MHz
SCLK Pulse-Width High
tCH
15
ns
SCLK Pulse-Width Low
tCL
15
ns
CS-Low to SCLK-High Setup
Time
tCSSO
15
ns
CS-High to SCLK-High Setup
Time
tCSS1
15
ns
SCLK-High to CS-Low Hold Time
tCSH0
10
ns


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