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CY28435 Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY28435
Description  Clock Generator for Intel Grantsdale Chipset
Download  23 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY28435 Datasheet(HTML) 10 Page - Cypress Semiconductor

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PRELIMINARY
CY28435
Document #: 38-07664 Rev. *B
Page 10 of 23
Crystal Recommendations
The CY28435 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28435 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 2 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
4
0
SMSW_SEL
Smooth switch select
0: select CPU_PLL
1: select SRC_PLL.
3
0
RESERVED
RESERVED, Set = 0
2
0
RESERVED
RESERVED, Set = 0
1
1
PCIF
Free running 33-MHz Output Drive Strength
0 = 2x, 1 = 1x
0
0
Recovery_N8
Watchdog Recovery Bit
Byte 15: Control Register 15
Bit
@Pup
Name
Description
7
0
Recovery N7
Watchdog Recovery Bit
6
0
Recovery N6
Watchdog Recovery Bit
5
0
Recovery N5
Watchdog Recovery Bit
4
0
Recovery N4
Watchdog Recovery Bit
3
0
Recovery N3
Watchdog Recovery Bit
2
0
Recovery N2
Watchdog Recovery Bit
1
0
Recovery N1
Watchdog Recovery Bit
0
0
Recovery N0
Watchdog Recovery Bit
Byte 16: Control Register 16
Bit
@Pup
Name
Description
7
1
REF1
REF1 Output Enable
0 = Disable, 1 = Enable
6
1
USB48_1
USB48_1 Output Enable
0 = Disable, 1 = Enable
5
0
SRC_FREQ_SEL
SRC Frequency selection
0: SRC frequency is selected via the FSE pin
1: SRC frequency is initially set to 167MHz.
4
0
RESERVED
RESERVED, Set = 0
3
0
SRC_SATA
SATA PLL Spread Spectrum Enable
0 = Spread off, 1 = Spread on
2
0
Prog_SRC_EN
Programmable SRC frequency enable
0 = disabled, 1 = enabled.
1
0
Prog_CPU_EN
Programmable CPU frequency enable
0 = disabled, 1 = enabled.
0
1
Watchdog Autorecovery Watchdog Autorecovery Mode
0 = Disable (Manual), 1= Enable (Auto)
Byte 14: Control Register 14 (continued)
Bit
@Pup
Name
Description


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