XR16C872 datasheet(5/60 Pages) EXAR

Part #	XR16C872

Description	DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

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Manufacturer	EXAR [Exar Corporation]

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XR16C872

5

Rev. 1.00

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PIN DESCRIPTION

Signal Type Definition. The following signal type definitions are from the 872 device point of view.

I

Standard input

O

Standard active output

OT24

Tri-state output

IOP14

Tri-state bi-directional input/output

IO24

Tri-state bi-directional input/output

HOST INTERFACE

A0-A15

2-15

I

ISA Bus Address. All 16 bits are used during PnP auto configuration

17,18

sequence with external EEPROM providing the resource data. In the

manual configuration mode A0-A10 are used for decoding COM1-4 and

LPT1-2 addresses. After auto or manual configuration, bits A0-A2 select

UART internal registers and A3-A10 are used to select UART A or B, or

the 1284 printer port.

D0-D7

30-21

IO24

ISA Data Bus. These are the eight three state data lines for transferring

data to or from the controlling CPU. D0 is the least significant bit and the

first data bit in a transmit or receive serial data stream.

AEN

19

I

Address Enable. Active high to validate A0-A15 address lines during Direct

Memory Access operation on the ISA bus. Connect to logic 0 when it is not used.

IOR#

99

I

Read Strobe. A logic 0 transition on this pin will request the contents of

an Internal register defined by address bits A0-A2 for either UART channels

A/B or A0-A1 for the printer port, be place onto D0-D7 data bus for a read

cycle by the CPU.

IOW#

100

I

Write Strobe. A logic 1 transition on this pin will transfer the data on the

data bus (D0-D7), as defined by either address bits A0-A2 for UART channels

A/B or A0-A1 for the printer port, into an internal register during a write cycle

from the CPU.

IRQ15

86

OT24

Interrupt Request Lines. These are three state active high interrupt lines to

IRQ12-10

87-89

controlling CPU when an interrupt request is generated by the UART

IRQ9

97

channel A/B or 1284 printer port.

IRQ3-7

92-96

DREQ5

78

OT24

DMA Request Channel 0,1,3 and 5. These are three state active high

DREQ3

79

outputs with internal weak pull down resistor. DMA request is used

DREQ1

80

by the 1284 parallel port during ECP and FIFO mode.

DREQ0

81

DACK5#

82

I

DMA Acknowledge Channel 0,1,3 and 5. These are active low inputs

DACK3#

83

and are used by the 1284 parallel port during ECP and FIFO mode.

DACK1#

84

DACK0#

85

Name

Pin #

Type

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