PS019101-1003

PRELIMINARY

I/O Connector (JP2)

eZ801905050MOD

eZ80190 Module Product Specification

5

Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification*

Pin #

Symbol

Pull

Up/Down*

Signal Direction Comments

1

Reserved

2

Reserved

3

Reserved

4

Reserved

5

TRSTN

Input

Reset for On-Chip Instrumentation (OCI);

not used with the eZ80190 Module.

6

Reserved

7

F91_WE

PU 10KΩ

Input

A Low enables a Write to on-chip Flash

memory. If this pin is unconnected, on-chip

Flash memory is write-protected; not used

with the eZ80190 Module.

8

Reserved

9

GND

10

3.3V supply input pin.

11

A6

Bidirectional

12

A0

Bidirectional

13

A10

Bidirectional

14

A3

Bidirectional

15

GND

16

3.3V supply input pin.

17

A8

Bidirectional

18

A7

Bidirectional

19

A13

Bidirectional

20

A9

Bidirectional

21

A15

Bidirectional

22

A14

Bidirectional

Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy

timing requirements for the CPU.

consumption and to reduce noise sensitivity.

To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down

Register.

All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.