16K x 16 Reprogrammable PROM
CY7C276
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 1991 – Revised December 1993
1CY 7C27 6
Features
• 0.8-micron CMOS for optimum speed/power
• High speed (for commercial and military)
— 25-ns access time
• 16-bit-wide words
• Three programmable chip selects
• Programmable output enable
• 44-pin PLCC and 44-pin LCC packages
• 100% reprogrammable in windowed packages
• TTL-compatible I/O
• Capable of withstanding greater than 2001V static dis-
charge
Functional Description
The CY7C276 is a high-performance 16K-word by 16-bit
CMOS PROM. It is available in a 44-pin PLCC/CLCC and a
44-pin LCC packages, and is 100% reprogrammable in win-
dowed packages. The memory cells utilize proven EPROM
floating gate technology and word-wide programming algo-
rithms.
The CY7C276 allows the user to independently program the
polarity of each chip select (CS2−CS0). This provides on-chip
decoding of up to eight banks of PROM. The polarity of the
asynchronous output enable pin (OE) is also programmable.
In order to read the CY7C276, all three chip selects must be
active and OE must be asserted. The contents of the memory
location addressed by the address lines (A13−A0) will become
available on the output lines (D15−D0). The data will remain on
the outputs until the address changes or the outputs are dis-
abled.
C276–1
16K x 16
PROGRAMMABLE
ARRAY
CS
DECODE
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LCC/PLCC/CLCC
Top View
C276–2
A13
A12
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A11
CS0
CS1
CS2
OE
1
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2
44 43 42 41 40
A13
A12
A11
A10
A9
VSS
VSS
A8
A7
A6
A5
D12
D11
D10
D9
D8
VSS
VCC
D7
D6
D5
D4
Logic Block Diagram
Pin Configuration
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