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PE83336 Datasheet(PDF) 3 Page - Peregrine Semiconductor Corp.

Part No. PE83336
Description  3.0 GHz Integer-N PLL for Low Phase Noise Applications
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Maker  PEREGRINE [Peregrine Semiconductor Corp.]
Homepage  http://www.peregrine-semi.com
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PE83336 Datasheet(HTML) 3 Page - Peregrine Semiconductor Corp.

 
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PE83336
Product Specification
PEREGRINE SEMICONDUCTOR CORP.
| http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 3 of 14
Pin No.
(44-lead
CQFJ)
Pin
Name
Interface
Mode
Type
Description
register data are transferred to the secondary register on S_WR or Hop_WR rising edge.
D4
Parallel
Input
Parallel data bus bit4
M4
Direct
Input
M Counter bit4
Sdata
Serial
Input
Binary serial data input. Input data entered MSB first.
D5
Parallel
Input
Parallel data bus bit5.
14
M5
Direct
Input
M Counter bit5.
Sclk
Serial
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
D6
Parallel
Input
Parallel data bus bit6.
15
M6
Direct
Input
M Counter bit6.
FSELS
Serial
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
D7
Parallel
Input
Parallel data bus bit7 (MSB).
16
Pre_en
Direct
Input
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
17
GND
ALL
Ground.
FSELP
Parallel
Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
18
A0
Direct
Input
A Counter bit0 (LSB).
Serial
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked
into the enhancement register on the rising edge of Sclk.
E_WR
Parallel
Input
Enhancement register write. D[7:0] are latched into the enhancement register on the rising
edge of E_WR.
19
A1
Direct
Input
A Counter bit1.
M2_WR
Parallel
Input
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of
M2_WR.
20
A2
Direct
Input
A Counter bit2.
Smode
Serial,
Parallel
Input
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
21
A3
Direct
Input
A Counter bit3 (MSB).
22
Bmode
ALL
Input
Selects direct interface mode (Bmode=1).
23
VDD
ALL
(Note 1)
Same as pin 1.
24
M1_WR
Parallel
Input
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of
M1_WR.
25
A_WR
Parallel
Input
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of
A_WR.
26
Hop_WR
Serial,
Parallel
Input
Hop write. The contents of the primary register are latched into the secondary register on
the rising edge of Hop_WR.
27
Fin
ALL
Input
Prescaler input from the VCO. 3.0 GHz max frequency.
28
Fin
ALL
Input
Prescaler complementary input. A bypass capacitor should be placed as close as possible
to this pin and be connected in series with a 50
resistor directly to the ground plane.
29
GND
ALL
Ground.


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