Product Specification

PE9763

Page 10 of 15

©2005 Peregrine Semiconductor Corp. All rights reserved.

Document No. 70-0140-01

│ UltraCMOS™ RFIC Solutions

While the E_WR input is “high” and the S_WR in-

enhancement register is double buffered to pre-

vent inadvertent control changes during serial

loading, with buffer capture of the serially entered

data performed on the falling edge of E_WR ac-

cording to the timing diagram shown in Figure 4.

After the falling edge of E_WR, the data provide

control bits as shown in Table 9 on page 10 will

have their bit functionality enabled by asserting

the

Enh input “low”.

Direct Interface Mode

Direct Interface Mode is selected by setting the

“Direct” input “high”.

Counter control bits are set directly at the pins as

shown in Table 7 and Table 8.

Table 7. Secondary Register Programming

Table 8. Auxiliary Register Programming

Table 9. Enhancement Register Programming

Interface

Mode

Enh

Pre_en

Addr

Direct

1

Pre_en

X

Serial*

1

0

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

Interface

Mode

Enh

Rsrv

Rsrv

Addr

Direct

1

X

X

X

Serial*

1

1

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

Interface

Mode

Enh

Reserved

Reserved

Power

Down

Counter

load

MSEL

output

LD Disable

Serial*

0

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge

.

MSB (first in)

MSB (first in)

(last in) LSB

(last in) LSB

(last in) LSB

MSB (first in)