9701-01 datasheet(6/13 Pages) PEREGRINE

Part #	9701-01

Description	3000 MHz UltraCMOS??Integer-N PLL Rad Hard for Space Applications

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Manufacturer	PEREGRINE [Peregrine Semiconductor Corp.]

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Product Specification

PE9701

Page 6 of 13

Document No. 70-0035-02

│ UltraCMOS™ RFIC Solutions

Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

Note 1:

Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk

specification.

Note 2:

CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p.

Note 3:

Parameter is guaranteed through characterization only, and is not tested.

Symbol

Parameter

Conditions

Min

Max

Units

Control Interface and Latches (see Figures 4, 5, 6)

fClk

Serial data clock frequency

(Note 1)

10

MHz

tClkH

Serial clock HIGH time

30

ns

tClkL

Serial clock LOW time

30

ns

tDSU

Sdata hold time after Sclk rising edge, D[7:0] set-up time to

M1_WR, M2_WR, A_WR, E_WR rising edge

10

ns

tDHLD

Sdata hold time after Sclk rising edge, D[7:0] hold time to

M1_WR, M2_WR, A_WR, E_WR rising edge

10

ns

tPW

S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width

30

ns

tCWR

Sclk rising edge to S_WR rising edge. S_WR, M1_WR,

M2_WR, A_WR falling edge to Hop_WR rising edge

30

ns

tCE

Sclk falling edge to E_WR transition

30

ns

tWRC

S_WR falling edge to Sclk rising edge. Hop_WR falling

edge to S_WR, M1_WR, M2_WR, A_WR rising edge

30

ns

tEC

E_WR transition to Sclk rising edge

30

ns

tMDO

MSEL data out delay after Fin rising edge

CL = 12 pf

8

ns

Main Divider (Prescaler Enabled)

Fin

Operating frequency

500

3000

MHz

PFin

Input level range

External AC coupling

-5

5

dBm

Main Divider (Prescaler Bypassed)

Fin

Operating frequency

50

300

MHz

PFin

Input level range

External AC coupling

-5

5

dBm

Reference Divider

fr

Operating frequency

(Note 3)

100

MHz

Pfr

Reference input power (Note 2)

Single-ended input

-2

dBm

Phase Detector

fc

Comparison frequency

(Note 3)

20

MHz

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