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PE9701 Datasheet(PDF) 5 Page - Peregrine Semiconductor Corp. |
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PE9701 Datasheet(HTML) 5 Page - Peregrine Semiconductor Corp. |
5 / 13 page Product Specification PE9701 Page 5 of 13 Document No. 70-0035-02 │ www.psemi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Table 2. Absolute Maximum Ratings Note 1: Periodically sampled, not 100% tested. Tested per MIL- STD-883, M3015 C2 Table 4. ESD Ratings Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 3. Operating Ratings Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter/Conditions Min Max Units VDD Supply voltage -0.3 4.0 V VI Voltage on any input -0.3 VDD + 0.3 V II DC into any input -10 +10 mA IO DC into any output -10 +10 mA Tstg Storage temperature range -65 150 °C Symbol Parameter/Conditions Min Max Units VDD Supply voltage 2.85 3.15 V TA Operating ambient temperature range -40 85 °C Symbol Parameter/Conditions Level Units VESD ESD voltage (Human Body Model) – Note 1 1000 V Symbol Parameter Conditions Min Typ Max Units IDD Operational supply current; Prescaler disabled Prescaler enabled VDD = 2.85 to 3.15 V 10 24 31 mA mA Digital Inputs: All except fr, Fin, Fin VIH High level input voltage VDD = 2.85 to 3.15 V 0.7 x VDD V VIL Low level input voltage VDD = 2.85 to 3.15 V 0.3 x VDD V IIH High level input current VIH = VDD = 3.15 V +70 µA IIL Low level input current VIL = 0, VDD = 3.15 V -1 µA Reference Divider input: fr IIHR High level input current VIH = VDD = 3.15 V +100 µA IILR Low level input current VIL = 0, VDD = 3.15 V -100 µA R0 Input: R0 IIHRO High level input current VIH = VDD = 3.15 V +70 µA IILRO Low level input current VIL = 0, VDD = 3.15 V -5 µA Counter and phase detector outputs: fc, fp. VOLD Output voltage LOW Iout = 6 mA 0.4 V VOHD Output voltage HIGH Iout = -3 mA VDD - 0.4 V Lock detect outputs: Cext, LD VOLC Output voltage LOW, Cext Iout = 100 µA 0.4 V VOHC Output voltage HIGH, Cext Iout = -100 µA VDD - 0.4 V VOLLD Output voltage LOW, LD Iout = 6 mA 0.4 V Charge Pump output: CP ICP - Source Drive current VCP = VDD / 2 -2.6 -2 -1.4 mA ICP – Sink Drive current VCP = VDD / 2 1.4 2 2.6 mA ICPL Leakage current 1.0 V < VCP < VDD – 1.0 V -1 1 µA ICP – Source vs. ICP Sink Sink vs. source mismatch VCP = VDD / 2, TA = 25° C 25 % ICP vs. VCP Output current magnitude variation vs. voltage V < VCP < VDD – 1.0 V TA = 25° C 25 % |
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