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4306-02 Datasheet(PDF) 8 Page - Peregrine Semiconductor Corp. |
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4306-02 Datasheet(HTML) 8 Page - Peregrine Semiconductor Corp. |
8 / 11 page Product Specification PE4306 Page 8 of 11 ©2003-2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0160-04 │ UltraCMOS™ RFIC Solutions B5 B4 B3 B2 B1 B0 C16 C8C4C2 C1 0 ↑↑ LSB (last in) MSB (first in) Table 7. 5-Bit Attenuator Serial Programming Register Map Table 9. Parallel Interface AC Characteristics Figure 18. Parallel Interface Timing Diagram Table 8. Serial Interface AC Characteristics Figure 17. Serial Interface Timing Diagram VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Note: The stop bit (B0) must always be low to prevent the attenuator from entering an unknown state. Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. LE Clock Data MSB LSB t LESUP t SDSUP t SDHLD t LEPW t PDSUP t PDHLD LE t LEPW Parallel Data C16:C1 Symbol Parameter Min Max Unit fClk Serial data clock frequency (Note 1) 10 MHz tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tLESUP LE set-up time after last clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns tSDSUP Serial data set-up time before clock rising edge 10 ns tSDHLD Serial data hold time after clock falling edge 10 ns Symbol Parameter Min Max Unit tLEPW LE minimum pulse width 10 ns tPDSUP Data set-up time before rising edge of LE 10 ns tPDHLD Data hold time after falling edge of LE 10 ns |
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