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4306 Datasheet(PDF) 7 Page - Peregrine Semiconductor Corp. |
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4306 Datasheet(HTML) 7 Page - Peregrine Semiconductor Corp. |
7 / 11 page Product Specification PE4306 Page 7 of 11 Document No. 70-0160-04 │ www.psemi.com ©2003-2008 Peregrine Semiconductor Corp. All rights reserved. Evaluation Kit The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE4306 DSA. J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and –VDD. If use of the internal negative voltage generator is desired, then connect –VDD (black banana plug) to ground. If an external –VDD is desired, then apply -3V. J1 should be connected to the LPT1 port of a PC with the supplied control cable. The evaluation software is written to operate the DSA in serial mode, so switch 7 (P/S) on the DIP switch SW1 should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. To evaluate the power up options, first disconnect the control cable from the evaluation board. The control cable must be removed to prevent the PC port from biasing the control pins. During power up with P/S=1 high and LE=0 or P/ S=0 low and LE=1, the default power-up signal attenuation is set to the value present on the five control bits on the five parallel data inputs (C1 to C16). This allows any one of the 32 attenuation settings to be specified as the power-up state. During power up with P/S=0 high and LE=0, the control bits are automatically set to one of four possible values presented through the PUP interface. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in the Table 6. Pin 20 is open and can be connected to any bias. Resistor on Pin 1 & 3 A 10 k Ω resistor on the inputs to pins 1 & 3 (Figure 16) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition. Figure 15. Evaluation Board Layout Figure 16. Evaluation Board Schematic Note: Resistors on pins 1 and 3 are required and should be placed as close to the part as possible to avoid package resonance and meet error specifications over frequency. 10 kohm Z=50 Ohm PS J5 SMA 1 10kohm J4 SMA 1 DATA C2 C1 CLK VCC C16 LE Z=50 Ohm U1 QFN4X4 1 2 3 4 5 11 12 13 14 15 C16 RFin DATA CLK LE GND VNEG PS RFout C8 C8 100 pF C4 Peregrine Specification 101/0112 Peregrine Specification 102/0144 |
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