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4274-02 Datasheet(PDF) 9 Page - Peregrine Semiconductor Corp. |
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4274-02 Datasheet(HTML) 9 Page - Peregrine Semiconductor Corp. |
9 / 12 page Preliminary Specification Peregrine Semiconductor Corp. ® │http://www.psemi.com Copyright © Peregrine Semiconductor Corp. 2005 PE4274 Page 9 of 12 Evaluation Kit The SPDT Switch Evaluation Kit facilitates customer evaluation of the PE4274 SPDT switch. The RF common port is connected through a 75 Ω transmission line to J2. Ports 1 and 2 are connected through 75 Ω transmission lines to J1 and J3. A through line connects F connectors J4 and J5. This transmission line can be used to estimate the PCB loss over the environmental conditions. J6 provides DC and digital inputs to the device. The board is composed of a four metal layer FR4 material with a total thickness of 0.062”. The transmission lines are hybrid microstrip/coplanar waveguide with ground plane (28 mil core, 21 mil width, 30 mil gap). The provided jumpers short the control pins to ground for logic low. With the jumper removed the control input rises to VDD for logic high through the 1 M Ω pull up resistor. These resistors will draw several microamps from VDD. They are not required for normal operation. Figure 14. Evaluation Board Layouts Figure 15. Evaluation Board Schematic J3 PE4274 MLPQ 20-Lead 4x4 mm GND GND GND GND GND GND GND GND RF1 RF2 J6-1 J6-5 J1 J2 J4 J5 1M Vdd J6-9 1M Vdd J6-13 |
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