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PE4256 Datasheet(PDF) 4 Page - Peregrine Semiconductor Corp. |
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PE4256 Datasheet(HTML) 4 Page - Peregrine Semiconductor Corp. |
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4 / 8 page  Product Specification PE4256 Page 4 of 8 ©2010-2011 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0144-04 │ UltraCMOS™ RFIC Solutions Evaluation Kit The SPDT Switch Evaluation Kit was designed to ease customer evaluation of the PE4256 SPDT switch. The RF common port (RFC) is connected through a 75 Ω transmission line to J2. Port 1 and Port 2 are connected through 75 Ω transmission lines to J1 and J3. A through transmission line connects F connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed with four metal layers in FR4 material with a total thickness of 0.062". The transmission lines were designed using a coplanar waveguide with ground plane (28 mil core, 21 mil width, 30 mil gap). J6 provides a means for controlling DC and digital inputs to the device. The provided jumpers short the package pin to ground for logic low. When the jumper is removed, the pin is pulled up to VDD for logic high. When the jumper is in place, 3 µA of current will flow through the 1 M Ω pull-up resistor. This extra current should not be attributed to the device. Proper PCB design is essential for full isolation performance. This evaluation board demonstrates good trace and ground management for minimum coupling and radiation. Figure 4. Evaluation Board Layouts Figure 5. Evaluation Board Schematic Peregrine Specification 102/0195~02A Peregrine Specification 101/0148~03A |
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