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4230-00 Datasheet(PDF) 2 Page - Peregrine Semiconductor Corp. |
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4230-00 Datasheet(HTML) 2 Page - Peregrine Semiconductor Corp. |
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2 / 7 page  Product Specification PE4230 Page 2 of 7 ©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0029-02 │ UltraCMOS™ RFIC Solutions Note 1: All RF pins must be DC blocked with an external series capacitor or held at 0 VDC. Table 2. Pin Descriptions Table 4. Absolute Maximum Ratings Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 3. DC Electrical Specifications Figure 3. Pin Configuration (Top View) 4230 1 2 3 4 8 7 6 5 V DD CTRL GND RFC RF1 GND GND RF2 Pin No. Pin Name Description 1 VDD Nominal +3V supply connection. 2 CTRL CMOS or TTL logic level: High = RFC to RF1 signal path Low = RFC to RF2 signal path 3 GND Ground connection. Traces should be physically short and connected to ground plane for best performance. 4 RFC Common RF port for switch.1 5 RF2 RF2 port.1 6 GND Ground Connection. Traces should be physically short and connected to ground plane for best performance. 7 GND Ground Connection. Traces should be physically short and connected to ground plane for best performance. 8 RF1 RF1 port.1 Symbol Parameter/Conditions Min Max Units VDD Power supply voltage -0.3 4.0 V VI Voltage on any input except for the CTRL input -0.3 VDD+ 0.3 V VCTRL Voltage on CTRL input 5.0 V TST Storage temperature range -65 150 °C TOP Operating temperature range -40 85 °C P IN Input power (50 Ω) 35 dBm VESD ESD voltage (Human Body Model) 250 V Parameter Min Typ Max Units VDD Power Supply Voltage 2.7 3.0 3.3 V IDD Power Supply Current (VDD = 3V, VCNTL = 3V) 29 35 µA Control Voltage High 0.7xVDD V Control Voltage Low 0.3xVDD V Control Voltage Signal Path CTRL = CMOS or TTL High RFC to RF1 CTRL = CMOS or TTL Low RFC to RF2 Table 5. Control Logic Truth Table The control logic input pin (CTRL) is typically driven by a 3-volt CMOS logic level signal, and has a threshold of 50% of VDD. For flexibility to support systems that have 5-volt control logic driv- ers, the control logic input has been designed to handle a 5-volt logic HIGH signal. (A minimal cur- rent will be sourced out of the VDD pin when the control logic input voltage level exceeds VDD.) Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC Electrical Specifications table. Exposure to absolute maximum ratings for extended periods may affect device reliability. |
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