Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

PE3340 Datasheet(PDF) 9 Page - Peregrine Semiconductor Corp.

Part No. PE3340
Description  3.0 GHz Integer-N PLL for Low Phase Noise Applications
Download  12 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  PEREGRINE [Peregrine Semiconductor Corp.]
Homepage  http://www.peregrine-semi.com
Logo 

PE3340 Datasheet(HTML) 9 Page - Peregrine Semiconductor Corp.

 
Zoom Inzoom in Zoom Outzoom out
 9 / 12 page
background image
PE3340
Advance Information
PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com
Copyright
© Peregrine Semiconductor Corp. 2004
Page 9 of 12
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
fp output
Drives the M counter output onto the Dout output.
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
fc output
Drives the reference counter output onto the Dout output
Bit 7
Reserved**
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U, and
PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc), PD_D
pulses “low”. If the divided reference leads the
divided VCO in phase or frequency (fc leads fp),
PD_U pulses “low”. The width of either pulse is
directly proportional to phase offset between the
two input signals, fp and fc.
The phase detector gain is equal to 2.70 V / 2
π,
which numerically yields 0.43 V / Radian.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses result
in an increase in VCO frequency and PD_D results
in a decrease in VCO frequency, for a positive Kv
VCO.
A lock detect output, LD is also provided, via the pin
Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn