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PE3335 Datasheet(PDF) 4 Page - Peregrine Semiconductor Corp.

Part No. PE3335
Description  3000 MHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications
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Maker  PEREGRINE [Peregrine Semiconductor Corp.]
Homepage  http://www.peregrine-semi.com
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PE3335 Datasheet(HTML) 4 Page - Peregrine Semiconductor Corp.

 
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Product Specification
PE3335
Page 4 of 15
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0049-02
│ UltraCMOS™ RFIC Solutions
28
23
Fin
ALL
Input
Prescaler complementary input. A bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50
Ω resistor
directly to the ground plane.
29
24
GND
ALL
Ground.
30
25
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
31
26
VDD-fp
ALL
(Note 1)
VDD for fp. Can be left floating or connected to GND to disable the fp output.
32
27
Dout
Serial,
Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on
Dout through enhancement register programming.
33
28
VDD
ALL
(Note 1)
Same as pin 1 (QFN48 pin 43).
34
29
Cext
ALL
Output
Logical “NAND” of PD_
U and PD_D terminated through an on chip, 2 kΩ
series resistor. Connecting Cext to an external capacitor will low pass filter
the input to the inverting amplifier used for driving LD.
35
30
VDD
ALL
(Note 1)
Same as pin 1 (QFN48 pin 43).
36
32
CP
ALL
Output
Charge pump current is sourced when fc leads fp and sinked when fc lags fp.
37
33, 34
NC
ALL
No connection.
38
35
VDD-fc
ALL
(Note 1)
VDD for fc can be left floating or connected to GND to disable the fc output.
39
36
fc
ALL
Output
Monitor pin for reference divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding VDD
pin 38.
40
31,37
GND
ALL
Ground.
41
38,39
GND
ALL
Ground.
42
40
fr
ALL
Input
Reference frequency input.
43
41
LD
ALL
Output
Lock detect and open drain logical inversion of Cext. When the loop is in lock,
LD is high impedance, otherwise LD is a logic low (“0”).
44
42
Enh
Serial,
Parallel
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Table 1. Pin Descriptions (continued)
Note 1:
All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
VDD-fp and VDD-fc are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc
outputs.
Note 2:
All digital input pins have 70 k
Ω pull-down resistors to ground.
Pin No.
(44-lead
PLCC)
Pin No.
(48-lead
QFN)
Pin
Name
Interface
Mode
Type
Description


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