PE3238 datasheet(4/15 Pages) PEREGRINE | 1500 MHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

Part No.	PE3238

Description	1500 MHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

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Product Specification

PE3238

Page 4 of 15

Document No. 70-0031-03

│ UltraCMOS™ RFIC Solutions

Table 1. Pin Descriptions (continued)

Note 1:

VDD pins 1, 11, 12, 23, 31, 33, 35 and 38 are connected by diodes and must be supplied with the same positive voltage level.

Note 2:

VDD pins 31 and 38 are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp

and fc outputs.

Pin No.

Pin Name

Interface Mode

Type

Description

ALL

Output

Monitor pin for main divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding VDD pin 31.

VDD-fp

ALL

(Note 2)

VDD for fp.

Dout

Serial, Parallel

Output

Data Out. The MSEL signal and the raw prescaler output are available on Dout

through enhancement register programming.

VDD

ALL

(Note 1)

Same as pin 1.

Cext

ALL

Output

Logical “NAND” of PD_

U and PD_D terminated through an on chip, 2 kohm series

resistor. Connecting Cext to an external capacitor will low pass filter the input to the

inverting amplifier used for driving LD.

VDD

ALL

(Note 1)

Same as pin 1.

PD_

ALL

Output

PD_

D is pulse down when f

p leads fc.

PD_

ALL

PD_

U is pulse down when f

c leads fp.

VDD-fc

ALL

(Note 2)

VDD for fc.

ALL

Output

Monitor pin for reference divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding VDD pin 38.

GND

ALL

Ground.

GND

ALL

Ground.

ALL

Input

Reference frequency input.

ALL

Output,

Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is

high impedance, otherwise LD is a logic low (“0”).

Enh

Serial, Parallel

Input

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

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