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PE3236 Datasheet(PDF) 4 Page - Peregrine Semiconductor Corp.

Part No. PE3236
Description  2200 MHz UltraCMOS-TM Integer-N PLL for Low Phase Noise Applications
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Maker  PEREGRINE [Peregrine Semiconductor Corp.]
Homepage  http://www.peregrine-semi.com
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PE3236 Datasheet(HTML) 4 Page - Peregrine Semiconductor Corp.

 
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Product Specification
PE3236
Page 4 of 15
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0026-03
│ UltraCMOS™ RFIC Solutions
Table 1. Pin Descriptions (continued)
Note 1:
VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
Note 2:
VDD pins 31 and 38 are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp
and fc outputs.
30
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
31
VDD-fp
ALL
(Note 2)
VDD for fp.
32
Dout
Serial, Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
33
VDD
ALL
(Note 1)
Same as pin 1.
34
Cext
ALL
Output
Logical “NAND” of PD_
U and PD_D terminated through an on chip, 2 kΩ series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
35
VDD
ALL
(Note 1)
Same as pin 1.
36
PD_
D
ALL
Output
PD_
D is pulse down when f
p leads fc.
37
PD_
U
ALL
PD_
U is pulse down when f
c leads fp.
38
VDD-fc
ALL
(Note 2)
VDD for fc.
39
fc
ALL
Output
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
40
GND
ALL
Ground.
41
GND
ALL
Ground.
42
fr
ALL
Input
Reference frequency input.
43
LD
ALL
Output,
OD
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
44
Enh
Serial, Parallel
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Pin No.
Pin Name
Interface Mode
Type
Description


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