853058AG

www.icst.com/products/hiperclocks.html

REV. A APRIL 13, 2004

10

Integrated

Circuit

Systems, Inc.

ICS853058

PRELIMINARY

An application schematic example of ICS853058 is shown in

Figure 5. The inputs can accept various types of differential sig-

nals. In this example, the inputs are driven by 3.3V LVPECL

drivers. The ICS853058 output is an LVPECL driver. An example

of LVPECL terminations is shown this schematic. Other termi-

nation approaches are available in the LVPECL Termination

Application Note. It is recommended at least one decoupling ca-

pacitor per power pin. The decoupling capacitor should be low

ESR and located as close as possible to the power pin.

R3

50

Zo = 50

Zo = 50

RD2

1K

C1

0.1u

To Logic

Input

pins

RD1

Not Install

R8

50

C2

0.1u

Zo = 50

U1

ICS853058

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

24

23

22

21

PCLK0

nPCLK0

PCLK1

nPCLK1

VCC

SEL0

SEL1

SEL2

PCLK2

nPCLK2

PCLK3

nPCLK3

nPCLK4

PCLK4

nPCLK5

PCLK5

GND

nQ0

Q0

VCC

PCLK7

nPCLK7

PCLK6

nPCLK6

3.3V

Zo = 50

R5

50

RU2

Not Install

R6

50

Zo = 50

Set Logic

Input to

'0'

3.3V

Logic Control Input Examples

R7

50

R1

50

R4

50

LVPECL

R9

50

Set Logic

Input to

'1'

R2

50

Zo = 50

RU1

1K

LVPECL

+

-

LVPECL

To Logic

Input

pins

3.3V

3.3V