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MPC7448ECS02AD Datasheet(PDF) 3 Page - NXP Semiconductors

Part # MPC7448ECS02AD
Description  MPC7448 Hardware Specifications Addendum for the MC7448Txxnnnnmx Series
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC7448ECS02AD Datasheet(HTML) 3 Page - NXP Semiconductors

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MPC7448 Hardware Specifications Addendum for the MC7448Txxnnnnmx Series, Rev. 2
Freescale Semiconductor
3
General Parameters
Table 7 provides the power consumption for the MPC7448 part numbers described by this document; see
Section 11.1, “Part Numbers Addressed by This Specification,” for more information. The MPC7448
RISC Microprocessor Hardware Specifications presents guidelines on the use of these parameters for
system design. For information on power consumption when dynamic frequency switching is enabled, see
Section 9.8.5, “Dynamic Frequency Switching (DFS),” in the hardware specifications.
The power consumptions provided in Table 7 represent the power consumption of each speed grade when
operated at the rated maximum core frequency (see Table 8). Freescale sorts devices by power as well as
by core frequency, and power limits for each speed grade are independent of each other. Each device is
tested at its maximum core frequency only. (Note that Deep Sleep Mode power consumption is
independent of clock frequency.) Operating a device at a frequency lower than its rated maximum is fully
supported provided the clock frequencies are within the specifications given in Table 8, and a device
operated below its rated maximum will have lower power consumption. However, inferences should not
be made about a device’s power consumption based on the power specifications of another (lower) speed
grade. For example, a 1400 MHz device operated at 1267 MHz will not exhibit the same power
consumption as a 1267 MHz device operated at 1267 MHz.
NOTE
The power consumption information in this table applies when the device
operates at the nominal core voltage indicated in Table 4. For power
consumption at derated core voltage conditions, see Section 5.3, “Voltage
and Frequency Derating.”
Table 4. Recommended Operating Conditions1
Characteristic
Symbol
Recommended Value
Unit
Notes
1000N MHz
1267N MHz3
Revision
Level C
1267N MHz3
Revision
Level D
1400N MHz3
1700L MHz
Core supply voltage
VDD
1.0 V
± 50 mV
1.1 V
± 50 mV
1.05 V
± 50 mV
1.15 V
± 50 mV
1.3 V
+20/-50 mV
V
PLL supply voltage
AVDD
1.0 V
± 50 mV
1.1 V
± 50 mV
1.05 V
± 50 mV
1.15 V
± 50 mV
1.3 V
+20/-50 mV
V2
Die-junction temperature
Tj
–40to105
–40to105
–40to105
–40to105
–40to105
•C
C
Notes:
1. These are the recommended and tested operating conditions. Some speed grades in addition support voltage derating; see
Section 5.3, “Voltage and Frequency Derating.” Proper device operation outside of these conditions and those specified in
Section 5.3, “Voltage and Frequency Derating,” is not guaranteed.
2. This voltage is the input to the filter discussed in Section 9.2.2, “PLL Power Supply Filtering,” in the hardware specifications
and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter.
3.
VDD and AVDD may be reduced in order to reduce power consumption if further maximum core frequency constraints are
observed. See Section 5.3, “Voltage and Frequency Derating,” for specific information.


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