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MIC21LV32 Datasheet(PDF) 39 Page - Microchip Technology |
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MIC21LV32 Datasheet(HTML) 39 Page - Microchip Technology |
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39 / 50 page  2021 Microchip Technology Inc. DS20006513A-page 39 MIC21LV32 6.0 PCB LAYOUT GUIDELINES PCB layout is critical to achieve reliable, stable and efficient performance. A ground plane is required to control EMI and minimize the inductance in power, signal and return paths. Use star ground technique between AGND and PGND, and minimize trace length for high-current paths. Follow these guidelines to ensure proper operation of the MIC21LV32 two-phase buck converter. 6.1 Integrated Circuit • The 2.2 µF ceramic capacitor, which is connected to the VDD pin, must be located right at the IC. The VDD pin is very noise-sensitive, so the place- ment of the capacitor is critical. Use wide traces to connect to the VDD, PVDD and PGND pins. • Connect a 2.2 µF ceramic capacitor to the EXTVDD pin, which must be located right at the IC. • Connect the Analog Ground pin (AGND) directly to the ground planes. Do not route the AGND pin to the PGND pad on the top layer. • Use thick traces and minimize trace length for the input and output power lines. • Keep the analog and power grounds separate, and connected at only one location. 6.2 Input Capacitor • Use parallel input capacitors to minimize effective ESR and ESL of input capacitor. • Place input capacitors next to the high-side power MOSFETs for each phase channel. • Place the input capacitors on the same side of the board and as close to the IC as possible. • Connect the VIN supply to the VIN pin through a 1.2Ω resistor and connect a 1 µF ceramic capaci- tor from the VIN pin to the PGND pin. Keep both the VIN pin and PGND connections short. • Place several vias to the ground plane, close to the input capacitors’ ground terminal. • Use either X7R or X5R dielectric input capacitors. Do not use Y5V or Z5U-type capacitors. • Do not replace the ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor. • In hot-plug applications, use an electrolytic bypass capacitor to limit the overvoltage spike seen on the input supply when power is suddenly applied. 6.3 Inductor • Keep the inductor connection to the switch node (SW1, SW2) short. • Do not route any digital lines underneath or close to the inductor. • Keep the switch node (SW1, SW2) away from the Feedback (FBS) pin. • Connect the CSPx pin and CSNx pin directly to the drain and source of the low-side power MOS- FET, respectively, and route the CSP and CSN traces together for each phase channel to accu- rately sense the voltage across the low-side MOSFET to achieve accurate current sensing. • To minimize noise, place a ground plane under the inductor. • The inductor can be placed on the opposite side of the PCB with respect to the IC. There should be sufficient vias on the power traces to conduct high current between the inductor and the IC and out- put load. It does not matter whether the IC or inductor is on the top or bottom, as long as there is enough heatsink and air flow to keep the power components within their temperature limits. Place the input and output capacitors on the same side of the board as the IC. 6.4 Output Capacitor • Use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal. • The feedback trace should be separate from the power trace and connected as close as possible to the output capacitor. Sensing a long high-current load trace can degrade the DC load regulation. 6.5 MOSFETs • MOSFET gate drive traces must be short and wide. The ground plane should be the connection between the MOSFET source and PGND. • Choose a low-side MOSFET with a high CGS/CGD ratio and a low internal gate resistance to minimize the effect of dV/dt inducted turn-on. • Use a 4.5V VGS rated MOSFET. Its higher gate threshold voltage is more immune to glitches than a 2.5V or 3.3V rated MOSFET. 6.6 VOUT Remote Sense • The remote sense traces must be routed close together or on adjacent layers to minimize noise pickup. The traces should be routed away from the switch node, inductors, MOSFETs and other high dV/dt or di/dt sources. 6.7 RC Snubber • Place the RC snubber on either side of the board and as close to the SW pin as possible. Note: To minimize EMI and output noise, follow these layout recommendations. |
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