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ICS85314BGI-01LF Datasheet(PDF) 11 Page - Integrated Circuit Systems |
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ICS85314BGI-01LF Datasheet(HTML) 11 Page - Integrated Circuit Systems |
11 / 19 page 85314BGI-01 www.icst.com/products/hiperclocks.html REV. E SEPTEMBER 23, 2005 11 Integrated Circuit Systems, Inc. ICS85314I-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FIGURE 4B. LVPECL OUTPUT TERMINATION FIGURE 4A. LVPECL OUTPUT TERMINATION TERMINATION FOR 3.3V LVPECL OUTPUTS |
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