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ICS85314AM-01 Datasheet(PDF) 9 Page - Integrated Circuit Systems |
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ICS85314AM-01 Datasheet(HTML) 9 Page - Integrated Circuit Systems |
9 / 15 page 85314AG-01 www.icst.com/products/hiperclocks.html REV. B JUNE 21, 2002 9 Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER PRELIMINARY APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V CC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V CC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. FIGURE 2 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT R2 1K V CC CLK_IN + - R1 1K C1 0.1uF V_REF The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V F OUT F IN 5 2 Zo Z o 5 2 Z o 3 2 Z o 3 2 Z o = 50Ω Z o = 50Ω RTT = 1 (V OH + VOL / VCC –2) –2 Z o Z o = 50Ω Z o = 50Ω 50 Ω 50 Ω RTT V CC - 2V F IN F OUT 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS FIGURE 3B - LVPECL OUTPUT TERMINATION FIGURE 3A - LVPECL OUTPUT TERMINATION |
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