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MCIMX6U4AVM08CB Datasheet(PDF) 39 Page - NXP Semiconductors

Part # MCIMX6U4AVM08CB
Description  i.MX 6Solo/6DualLite Applications Processors for Industrial Products
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MCIMX6U4AVM08CB Datasheet(HTML) 39 Page - NXP Semiconductors

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Electrical Characteristics
i.MX 6Solo/6DualLite Applications Processors for Industrial Products, Rev. 9, 11/2018
NXP Semiconductors
39
4.6.2
General Purpose I/O (GPIO) DC Parameters
Table 22 shows DC parameters for GPIO pads. The parameters in Table 22 are guaranteed per the
operating ranges in Table 8, unless otherwise noted.
4.6.3
DDR I/O DC Parameters
The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes.
4.6.3.1
LPDDR2 Mode I/O DC Parameters
For details on supported DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller
(MMDC).
Table 22. GPIO DC Parameters
Parameter
Symbol
Test Conditions
Min
Max
Units
High-level output voltage1
1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.
Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
VOH
Ioh= -0.1mA (DSE=001,010)
Ioh= -1mA
(DSE=011,100,101,110,111)
OVDD - 0.15
V
Low-level output voltage1
VOL
Iol= 0.1mA (DSE=001,010)
Iol= 1mA
(DSE=011,100,101,110,111)
—0.15
V
High-Level input voltage1,2
2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
VIH
0.7
× OVDD
OVDD
V
Low-Level input voltage1,2
VIL
0
0.3
× OVDD
V
Input Hysteresis (OVDD= 1.8V)
VHYS_LowVDD
OVDD=1.8V
250
mV
Input Hysteresis (OVDD=3.3V
VHYS_HighVDD
OVDD=3.3V
250
mV
Schmitt trigger VT+2,3
3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
VTH+
0.5
× OVDD
mV
Schmitt trigger VT-2,3
VTH-
0.5
× OVDD mV
Pull-up resistor (22_k
Ω PU)
RPU_22K
Vin=0V
212
uA
Pull-up resistor (22_k
Ω PU)
RPU_22K
Vin=OVDD
1
uA
Pull-up resistor (47_k
Ω PU)
RPU_47K
Vin=0V
100
uA
Pull-up resistor (47_k
Ω PU)
RPU_47K
Vin=OVDD
1
uA
Pull-up resistor (100_k
Ω PU)
RPU_100K
Vin=0V
48
uA
Pull-up resistor (100_k
Ω PU)
RPU_100K
Vin=OVDD
1
uA
Pull-down resistor (100_k
Ω PD)
RPD_100K
Vin=OVDD
48
uA
Pull-down resistor (100_k
Ω PD)
RPD_100K
Vin=0V
1
uA
Input current (no PU/PD)
IIN
VI = 0, VI = OVDD
-1
1
uA
Keeper Circuit Resistance
R_Keeper
VI = 0.3
× OVDD, VI = 0.7 × OVDD
105
175
k
Ω


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