84321AYI

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 10, 2003

10

Integrated

Circuit

Systems, Inc.

ICS84321I

The schematic of the ICS84321I layout example used in this lay-

out guideline is shown in

Figure 5A. The ICS84321I recommended

PCB board layout for this example is shown in

Figure 5B. This

layout example is used as a general guideline. The layout in the

actual system will depend on the selected component types, the

density of the components, the density of the traces, and the

stack up of the P.C. board.

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS84321I provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 4 illustrates how

a 24

Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V

24

Ω

V

CCA

10

µF

.01

µF

3.3V

.01

µF

V

CC

R4

84

+

-

VCCA

U1

ICS84321

1

2

3

4

5

6

7

8

17

18

19

20

21

22

23

24

M5

M6

M7

M8

N0

N1

nc

VEE

MR

S_CLOCK

S_DATA

S_LOAD

VCCA

nXTAL_SEL

T_CLK

XTAL2

R1

125

S_CLOCK

TL2

Zo = 50 Ohm

C15

0.1u

R7

24

VCC

C16

10u

IN-

R3

125

XTAL_SEL

TL1

Zo = 50 Ohm

C11

0.01u

C14

0.1u

IN+

C2

C1

S_LOAD

R2

84

S_DATA

VCC

REF_IN

X1