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ICS650G-40LF Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS650G-40LF Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 6 page ETHERNET SWITCH CLOCK SOURCE MDS 650-40 C 2 Revision 060705 In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com ICS650-40 Pin Assignment Output Select Table (MHz) Pin Descriptions 1 2 3 X2 4 VDD 5 6 7 8 VDDOA S1 OE GND 16 X1/ICLK GND 15 14 13 12 11 10 9 16-pin (173 mil) TSSOP CLKB CLKA VDDOB GND S0 GND VDD VDD S1 S0 CLKA (MHz) CLKB (MHz) 0 0 127 127 0 1 133 133 1 0 157 157 1 1 189 189 Pin Number Pin Name Pin Type Pin Description 1 X1/ICLK Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 VDDOA Power Connect to +2.5 V or +3.3 V. For clock output buffer A only. 5 CLKA Output Clock A output with weak pull-down resistor. 6 CLKB Output Clock B output with weak pull-down resistor. 7 VDDOB Power Connect to +2.5 V or +3.3 V. For clock output buffer B only. 8 GND Power Connect to ground. 9 S0 Input Select pin 0. 10 S1 Input Select pin 1. 11 VDD Power Connect to +3.3 V. 12 VDD Power Connect to +3.3 V. 13 GND Power Connect to ground. 14 OE Input Output enable tri-states outputs and device is not shut down. Internal pull-up resistor. 15 GND Power Connect to ground. 16 X2 Output Crystal connection. Leave unconnected for clock input. |
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