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MCIMX6U4AVM08AD Datasheet(PDF) 8 Page - NXP Semiconductors |
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MCIMX6U4AVM08AD Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 169 page  i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 8 NXP Semiconductors Introduction — Four Pulse Width Modulators (PWM) — System JTAG Controller (SJC) — GPIO with interrupt capabilities — 8x8 Key Pad Port (KPP) — Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx — Two Controller Area Network (FlexCAN), 1 Mbps each — Two Watchdog timers (WDOG) — Audio MUX (AUDMUX) — MLB (MediaLB) provides interface to MOST Networks (MOST25, MOST50, MOST150) with the option of DTCP cipher accelerator The i.MX 6Solo/6DualLite processors integrate advanced power management unit and controllers: • Provide PMU, including LDO supplies, for on-chip resources • Use Temperature Sensor for monitoring the die temperature • Support DVFS techniques for low power modes • Use SW State Retention and Power Gating for Arm and MPE • Support various levels of system power modes • Use flexible clock gating control scheme The i.MX 6Solo/6DualLite processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks. The i.MX 6Solo/6DualLite processors incorporate the following hardware accelerators: • VPU—Video Processing Unit • IPUv3H—Image Processing Unit version 3H • GPU3Dv5—3D Graphics Processing Unit (OpenGL ES 2.0) version 5 • GPU2Dv2—2D Graphics Processing Unit (BitBlt) • PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to support the EPD display applications. • ASRC—Asynchronous Sample Rate Converter Security functions are enabled and accelerated by the following hardware: • Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.) • SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features. • CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash engines, 16 KB secure RAM, and True and Pseudo Random Number Generator (NIST certified). • SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock • CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy. |
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