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MCIMX6U4AVM08AD Datasheet(PDF) 58 Page - NXP Semiconductors |
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MCIMX6U4AVM08AD Datasheet(HTML) 58 Page - NXP Semiconductors |
58 / 169 page i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 58 NXP Semiconductors Electrical Characteristics Figure 18. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=0 4.9.3.4 General EIM Timing-Asynchronous Mode Figure 19 through Figure 23, and Table 43 help you determine timing parameters relative to the chip select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing parameters mentioned above. Asynchronous read & write access length in cycles may vary from what is shown in Figure 19 through Figure 22 as RWSC, OEN and CSN is configured differently. See the i.MX 6Solo/6DualLite Reference Manual (IMX6SDLRM) for the EIM programming model. Figure 19. Asynchronous Memory Read Access (RWSC = 5) Last EIM_BCLK EIM_ADDRxx/ EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B EIM_CSx_B Address V1 Data Valid Address EIM_ADxx WE5 WE6 WE7 WE14 WE15 WE10 WE11 WE12 WE13 WE18 WE19 WE4 Last Valid Address Address V1 D(V1) EIM_ADDRxx/ EIM_DATAxx[7:0] EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B EIM_CSx_B Next Address WE39 WE35 WE37 WE32 WE36 WE38 WE43 WE40 WE31 WE44 INT_CLK start of access end of access MAXDI MAXCSO MAXCO EIM_ADxx |
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