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IXLD02SI Datasheet(PDF) 3 Page - IXYS Corporation

Part # IXLD02SI
Description  Differential 2A Ultra Fast Laser Diode Driver
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Manufacturer  IXYS [IXYS Corporation]
Direct Link  http://www.ixys.com
Logo IXYS - IXYS Corporation

IXLD02SI Datasheet(HTML) 3 Page - IXYS Corporation

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IXLD02SI
Name
Definition
Min
Typ
Max
Units
Test Conditions
VDD Logic supply input voltage
4.5
5.5
V
VDDA Analog bias supply input voltage
4.5
5.5
V
VTT Internal bias voltage input
2
VDDA/2
3
V
Measured with Zin>10meg DVM.
RVTT VTT terminal resistance
30
50
70
Kohms Measured with VDDin=VDDA=0V.
IIBI
Internal bias current input range
10
100
300
uA
External current source between
VDDA and IBI terminal.
VIBI
Measured IBI terminal voltage
0.6
1.7
V
IIBI=100uA.
IIPW
Pulse width programming current input
range.
-1
100
400
uA
External current source between
VDDA and IPW terminal.
VIPW Measured IPW terminal voltage
0.6
1.7
V
IIPW=100uA.
tPW
IOUT=2A peak, Output current pulse width
1
ns
IIBI=400uA, IIPW=300uA, IIOP=1mA.
IIOP
OUT and OUTB output current, IOUT,
programming current.
0
1
3
mA
External current source between
VDDA and IBI terminals.
VIOP Measured IOP terminal voltage
0.6
1.7
V
IBI=100uA.
IOUT/IIOP Output current to programming current gain
1800
2000
2200
I/I
IIOP=1mA, VOUT=VOUTB=10V.
VIH
Logic input high threshold for PDN, RST, &
FIN inputs.
0.7*VDD
V
VIL
Logic input high threshold for PDN, RST, &
FIN inputs.
.3*VDD
V
ILIN
Logic input bias current for PDN, RST, &
FIN inputs.
-10
10
uA
For logic inputs, PDN, RST, & FIN
held at:-0.5V<VLIN<VDD
tPDN
IXLD02 power down delay, VPDN logical low
to high transition.
50
ns
IXLD02 power up delay, VPDN logical high to
low transition.
30
ns
tRST
IXLD02 reset logic delay, VRST logical low to
high transition.
100
ns
IXLD02 reset logic delay, VRST logical low to
high transition.
100
ns
tFIN
IXLD02 pulse frequency input, VFIN, logical
low to high transition to IOUT pulse delay.
50
ns
IIBI=400uA, IIPW=300uA, IIOP=1mA..
fFINmax Maximum pulse frequency, FIN, logic input.
17
MHz IIBI=400uA, IIPW=300uA, IIOP=1mA..
IOUT
Peak true pulse current output.
1.6
2
2.4
Amps IIBI=400uA, IIPW=300uA, IIOP=1mA.,
VOUT=VOUTB=10V.
tR
Rise time
600
ps
tF
Fall time
600
ps
TONDLY On-time propagation delay
30
ns
TOFFDLY Off-time propagation delay
30
ns
PWmax Pulse width maximum
>1
us
Tj
Jitter
<300
ps
VOUT OUT terminal voltage
8
12
V
IIBI=400uA, IIPW=300uA, IIOP=1mA,
1.4A<IOUT<2.6A peak.
IOUTB Minimum complement pulse current output.
0
0.2
0.4
Amps IIBI=400uA, IIPW=300uA, IIOP=1mA.,
VOUT=VOUTB=10V.
VOUTB OUTB terminal voltage
8
12
V
IIBI=400uA, IIPW=300uA, IIOP=1mA,
0A<IOUT<0.6A minimum.
Recommended Operating Conditions
Unless otherwise noted, VDD=VDDA=5V, T
C=25C


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