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EM6812WP27 Datasheet(PDF) 3 Page - EM Microelectronic - MARIN SA |
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EM6812WP27 Datasheet(HTML) 3 Page - EM Microelectronic - MARIN SA |
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3 / 81 page  R EM6812 Copyright © 2005, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com Table of contents 1 EM6812 at a glance 2 2 Circuit Connectivity 5 2.1 Terminal usage 6 2.2 Programming connections 7 3 Operating modes 8 3.1 Active mode 8 3.2 Standby Mode 8 3.3 Sleep Mode 8 3.4 System registers 9 4 Program Memory 10 4.1 Memory miss 10 5 Data Memory 12 5.1 SRAM 12 5.2 General Purpose Registers, 16 Bytes 13 5.3 Dual Port RAM 13 5.3.1 CPU R/W access to DPR 13 5.3.2 External Write Access to DPR 14 5.3.3 Read Access from DPR 14 5.3.4 Conflict handling 15 5.3.5 Register overview 15 6 CPU 16 7 Reset Controller 17 7.1 Basic features 17 7.1.1 Reset functions registers 18 7.2 POR and PowerCheck 19 7.3 Reset Pad 20 7.4 PortA Input Reset 20 7.5 BrownOut reset 21 7.5.1 BO Timings 21 7.6 Watchdog 22 7.6.1 Watchdog counter 22 7.6.2 Lock/Unlock 22 8 Clock management 23 8.1 Basic features 23 8.1.1 Overview 23 8.2 High frequency clock source 24 8.2.1 RC oscillator 24 8.2.2 High frequency external clock 25 8.3 Low frequency clock source: 26 8.3.1 Crystal oscillator 26 8.3.2 Low frequency external clock 27 8.3.3 Data input on OscOut 27 8.4 Clock synchronization 27 8.5 CPU clock selection 28 8.6 Peripheral clocks generation 28 8.6.1 Prescaler2 (10 stages) 29 8.6.2 Prescaler1 (15 stages) 30 8.7 RC clock trimming with Xtal oscillator 31 8.8 Registers overview 32 9 Supply Voltage Level Detector (SVLD) 33 10 Port A 34 10.1 Basic features 34 10.1.1 Overview 35 10.1.2 Register map, PA IO functions 36 10.1.3 IO Operation 37 10.2 Port A Interrupt requests 38 10.2.1 Debouncer 38 10.3 Reset and Wake-up 39 10.3.1 Register map 40 10.3.2 Input splitting 40 10.3.3 Actions 40 10.3.4 Condition match 40 10.3.5 Don’t care bits 41 10.3.6 Debouncer 41 10.4 Oscillation Loop 41 10.4.1 Inverter function 41 10.5 Dual Port RAM interface 41 11 Port B 42 11.1 Basic features 42 11.1.1 Special function priority handling 42 11.1.2 Overview 43 11.2 Register map, PB IO functions 44 11.3 Normal IO operation 45 11.4 Special IO operation 45 11.4.1 Frequency Output 45 11.4.2 SPI outputs 46 11.4.3 SPI inputs 46 11.4.4 Dual Port RAM terminals 46 12 Serial Port Interface 47 12.1 Basic features: 47 12.1.1 Overview: 47 12.1.2 SPI terminal configuration 48 12.2 Functionality 48 12.2.1 Master and Slave modes 48 12.2.2 Fix data stream Output (Auto-Start) 48 12.2.3 SPI Interruptions 48 12.2.4 SPI edge and synchronization selection 49 12.2.5 SPI start-up 49 12.2.6 MSB or LSB first selection 49 12.3 Registers overview: 50 13 Timers 51 13.1 Basic features: 51 13.2 Functionality 52 13.2.1 Auto-Reload mode 52 13.2.2 Zero-Stop mode 53 13.2.3 Start control system 54 13.2.4 Stopping the timer 57 13.2.5 Clock selection 57 13.2.6 PWM and Frequency generation 57 13.2.7 16-bits configuration 58 13.2.8 Interrupts 59 13.3 Recommended programming order 60 13.4 Registers overview: 60 13.4.1 General configuration registers 60 13.4.2 Timer1 configuration 61 13.4.3 Timer2 configuration 62 13.4.4 Timer3 configuration 63 13.4.5 Timer4 configuration 64 14 Interruptions 65 14.1 Basic features 65 14.2 Interrupt acquisition 66 14.2.1 Interrupt acquisition masking. 67 14.2.2 Interrupt acquisition Clearing 67 14.2.3 Register map, Interrupt acquisition 67 14.3 CPU Interrupt and Event handling 68 14.3.1 Interrupt priority 68 14.3.2 CPU Status register 69 14.3.3 CPU Status register pipeline exception 69 14.3.4 Processor vector table 70 14.3.5 Context Saving 70 |
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