ICS525R-11T datasheet(7/9 Pages) ICST

Part #	ICS525R-11T

Description	User Configurable Clock

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Manufacturer	ICST [Integrated Circuit Systems]

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User Configurable Clock

MDS 525-01/02/11/12 Q

7

Revision 101105

Integrated Circuit Systems, Inc.

● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS525-01/02/11/12

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V

Short Circuit Current

CLK and REF outputs

±55

mA

Input Capacitance

CIN

V, R, S pins and pin 19

4

pF

On-chip Pull-up Resistor

RPU

V, R, S pins and pin 19

270

k

Ω

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

FIN

Crystal input

5

27

MHz

Clock input

2

50

MHz

Output Clock Rise Time

0.8 to 2.0 V

1

ns

Output Clock Fall Time

2.0 to 0.8 V

1

ns

Output Clock Duty Cycle, OD =

2, 4, 6, 8, or 10

At VDD/2

45

49 to

51

55

%

Output Clock Duty Cycle, OD =

3, 5, 7, or 9

At VDD/2

40

60

%

Output Clock Duty Cycle, OD =

1 (-02 and -12 only)

At VDD/2

35

65

Power-down Time, PD low to

clocks stopped

50

ns

Power-up Time, PD high to

clocks stable

10

ms

Absolute Clock Period Jitter,

ICS525-01, Note 2

tja

Deviation from mean

±140

ps

One Sigma Clock Period Jitter,

ICS525-01, Note 2

tjs

One Sigma

45

ps

Absolute Clock Period Jitter,

ICS525-02, Note 2

tja

Deviation from mean

±85

ps

One Sigma Clock Period Jitter,

ICS525-02, Note 2

tjs

One Sigma

30

ps

Absolute Clock Period Jitter,

ICS525-11, Note 2

tja

Deviation from mean

±160

ps

One Sigma Clock Period Jitter,

ICS525-11, Note 2

tjs

One Sigma

40

ps

Absolute Clock Period Jitter,

ICS525-12, Note 2

tja

Deviation from mean

±160

ps

One Sigma Clock Period Jitter,

ICS525-12, Note 2

tjs

One Sigma

40

ps

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

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