PRELIMINARY
CYP15G0403DXB
CYV15G0403DXB
Document #: 38-02065 Rev. *C
Page 10 of 43
ADDR[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[7:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.[5] Table9 lists
the configuration latches within the device, and the initialization value of the
latches upon the assertion of RESET. Table 10 shows how the latches are mapped
in the device.
DATA[7:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus. The DATA[7:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.[5 ] Table9 lists the configu-
ration latches within the device, and the initialization value of the latches upon the
assertion of RESET. Table 10 shows how the latches are mapped in the device.
Internal Device Configuration Latches
RFMODE[A..D][1:0]
Internal Latch[6]
Reframe Mode Select.
FRAMCHAR[A..D]
Internal Latch[6]
Framing Character Select.
DECMODE[A..D]
Internal Latch[6]
Receiver Decoder Mode Select.
DECBYP[A..D]
Internal Latch[6]
Receiver Decoder Bypass.
RXCKSEL[A..D]
Internal Latch[6]
Receive Clock Select.
RXRATE[A..D]
Internal Latch[6]
Receive Clock Rate Select.
SDASEL[A..D][1:0]
Internal Latch[6]
Signal Detect Amplitude Select.
ENCBYP[A..D]
Internal Latch[6]
Transmit Encoder Bypassed.
TXCKSEL[A..D]
Internal Latch[6]
Transmit Clock Select.
TXRATE[A..D]
Internal Latch[6]
Transmit PLL Clock Rate Select.
RFEN[A..D]
Internal Latch[6]
Reframe Enable.
RXPLLPD[A..D]
Internal Latch[6]
Receive Channel Power Control.
RXBIST[A..D]
Internal Latch[6]
Receive Bist Disabled.
TXBIST[A..D]
Internal Latch[6]
Transmit Bist Disabled.
OE2[A..D]
Internal Latch[6]
Differential Serial Output Driver 2 Enable.
OE1[A..D]
Internal Latch[6]
Differential Serial Output Driver 1 Enable.
PABRST[A..D]
Internal Latch[6]
Transmit Clock Phase Alignment Buffer Reset.
GLEN[11..0]
Internal Latch[6]
Global Latch Enable.
FGLEN[2..0]
Internal Latch[6]
Force Global Latch Enable.
Factory Test Modes
LTEN1
LVTTL input,
internal pull-down
Factory Test 1. LTEN1 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
SCANEN2
LVTTL input,
internal pull-down
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left
as a NO CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull-down
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
Note:
6.
See Device Configuration and Control Interface for detailed information on the internal latches.
Pin Definitions (continued)
CYP(V)15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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