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ICS527-02 Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS527-02 Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 8 page Clock Slicer User Configurable PECL Input Zero Delay Buffer MDS 527-02 F 4 Revision 022806 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS527-02 the correct clock when mounted on the board. It is also possible to connect the inputs to parallel I/O ports in order to switch frequencies. The output of the ICS527-02 can be determined by the following simple equation: Where: Reference Divider Word (RDW) = 0 to 127 Feedback Divider Word (FDW) = 0 to 127 FB Frequency is the same as either CLK1 or CLK2 depending on feedback connection Also, the following operating ranges should be observed: S0 and S1 should be selected depending on the frequency of CLK1. The table on page 2 gives the ranges. The dividers are expressed as integers. For example, if a 50 MHz output on CLK1 is desired from a 40 MHz input, the reference divider word (RDW) should be 2 and the feedback divider word (FDW) should be 3 which gives the required 5/4 multiplication. If multiple choices of dividers are available, then the lowest numbers should be used. In this example, the output divide (OD) should be selected to be 2. Then R6:R0 is 0000010, F6:F0 is 0000011 and S1:S0 is 00. Also, this example assumes CLK1 is connected to FBIN. If you need assistance determining the optimum divider settings, please send an e-mail to mk-support@icst.com with the desired input clock and the desired output frequency. Typical Example The layout diagram below will produce the waveforms shown on the right. Note: The series termination resistor is located before the feedback trace FB Frequency Input Frequency FDW 2 + RDW 2 + ------------------------ × = 300kHz Input Frequency RDW 2 + ------------------------------------------- 20 MHz << 40 MHz PECLIN 50 MHz CLK1 SYNC CLK2 PECLIN FBIN PECLIN F6 F5 GND F4 OECLK2 F0 F1 F2 F3 CLK1 CLK2 GND S1 VDD R0 VDD DIV2 S0 R2 R1 R5 R6 R4 R3 PECLIN PDTS 50 MHz SYNC 33 Ω 33 Ω 0.01 µF 40 MHz 40 MHz 0.01 µF VDD |
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