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ICS525R-03I Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS525R-03I Datasheet(HTML) 6 Page - Integrated Circuit Systems |
6 / 7 page PECL Input OSCaR™ User Configurable Clock MDS 525-03 H 6 Revision 010906 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS525-03 AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency FIN Clock input 0.5 250 MHz Output Frequency, VDD=4.5 to 5 V FOUT OD = 1 1 250 MHz Output Frequency, VDD=3.0 to 3.6 V FOUT OD = 1 1 200 MHz Output Clock Rise Time, CMOS clock 0.8 to 2.0 V 1 ns Output Clock Fall Time, CMOS clock 2.0 to 0.8 V 1 ns Output Clock Duty Cycle, even output dividers at VDD/2 45 55 % Output Clock Duty Cycle, odd output dividers at VDD/2 40 60 % Absolute Clock Period Jitter tja Deviation from mean ±350 ps One Sigma Clock Period Jitter tjs One Sigma 125 ps |
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