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CLRC66103HNT Datasheet(PDF) 85 Page - NXP Semiconductors |
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CLRC66103HNT Datasheet(HTML) 85 Page - NXP Semiconductors |
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85 / 152 page  NXP Semiconductors CLRC661 High performance NFC frontend CLRC661 plus Bit Symbol Description 7 TxWaitStart If cleared, the TxWait time is starting at the End of the send data (TX). If set, the TxWait time is starting at the End of the received data (RX). 6 TxWaitEtu If cleared, the TxWait time is TxWait × 16/13.56 MHz. If set, the TxWait time is TxWait × 0.5 / DBFreq (DBFreq is the frequency of the bit stream as defined by TxDataCon). 5 to 3 TxWait High Bit extension of TxWaitLo. TxWaitCtrl bit 5 is MSB. 2 to 0 TxStopBitLength Defines stop-bits and EGT (= stop-bit + extra guard time EGT) to be sent: 0h: no stop-bit, no EGT 1h: 1 stop-bit, no EGT 2h: 1 stop-bit + 1 EGT 3h: 1 stop-bit + 2 EGT 4h: 1 stop-bit + 3 EGT 5h: 1 stop-bit + 4 EGT 6h: 1 stop-bit + 5 EGT 7h: 1 stop-bit + 6 EGT Note: This is only valid for ISO/IEC14443 Type B Table 145. TXWaitCtrl bits 9.10.5 TxWaitLo Bit 7 6 5 4 3 2 1 0 Symbol TxWaitLo Access rights r/w Table 146. TxWaitLo register (address 32h) Bit Symbol Description 7 to 0 TxWaitLo Defines the minimum time between receive and send or between two send data streams Note: TxWait is a 11bit register (additional 3 bits are in the TxWaitCtrl register)! See also TxWaitEtu and TxWaitStart. Table 147. TxWaitLo bits 9.11 FrameCon Bit 7 6 5 4 3 2 1 0 Symbol TxParityEn RxParityEn - - StopSym StartSym Access rights r/w r/w RFU RFU r/w r/w Table 148. FrameCon register (address 33h) CLRC661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.7 — 23 June 2021 COMPANY PUBLIC 456937 85 / 152 |
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