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CLRC66103HNT Datasheet(PDF) 63 Page - NXP Semiconductors |
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CLRC66103HNT Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 152 page  NXP Semiconductors CLRC661 High performance NFC frontend CLRC661 plus Bit Symbol Description 7 Set 1: writing a 1 to a bit position 5..0 sets the interrupt request 0: Writing a 1 to a bit position 5..0 clears the interrupt request 6 GlobalIRQ Set, if an enabled IRQ occurs. 5 LPCD_IRQ Set if a card is detected in Low-power card detection sequence. 4 Timer4IRQ Set to logic 1 when Timer4 has an underflow. 3 Timer3IRQ Set to logic 1 when Timer3 has an underflow. 2 Timer2IRQ Set to logic 1 when Timer2 has an underflow. 1 Timer1IRQ Set to logic 1 when Timer1 has an underflow. 0 Timer0IRQ Set to logic 1 when Timer0 has an underflow. Table 59. IRQ1 bits 9.5.3 IRQ0En register Interrupt request enable register for IRQ0. This register allows defining if an interrupt request is processed by the CLRC661. Bit 7 6 5 4 3 2 1 0 Symbol IRQ_Inv Hi AlertIRQEn LoAlertIRQEn IdleIRQEn TxIRQEn RxIRQEn ErrIRQEn RxSOF IRQEn Access rights r/w r/w r/w r/w r/w r/w r/w r/w Table 60. IRQ0En register (address 08h) Bit Symbol Description 7 IRQ_Inv Set to one the signal of the IRQ pin is inverted 6 Hi AlerIRQEn Set to logic 1, it allows the High Alert interrupt Request (indicated by the bit HiAlertIRQ) to be propagated to the GlobalIRQ 5 Lo AlertIRQEn Set to logic 1, it allows the Low Alert Interrupt Request (indicated by the bit LoAlertIRQ) to be propagated to the GlobalIRQ 4 IdleIRQEn Set to logic 1, it allows the Idle interrupt request (indicated by the bit IdleIRQ) to be propagated to the GlobalIRQ 3 TxIRQEn Set to logic 1, it allows the transmitter interrupt request (indicated by the bit TxtIRQ) to be propagated to the GlobalIRQ 2 RxIRQEn Set to logic 1, it allows the receiver interrupt request (indicated by the bit RxIRQ) to be propagated to the GlobalIRQ 1 ErrIRQEn Set to logic 1, it allows the Error interrupt request (indicated by the bit ErrorIRQ) to be propagated to the GlobalIRQ 0 RxSOFIRQEn Set to logic 1, it allows the RxSOF interrupt request (indicated by the bit RxSOFIRQ) to be propagated to the GlobalIRQ Table 61. IRQ0En bits 9.5.4 IRQ1En Interrupt request enable register for IRQ1. CLRC661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.7 — 23 June 2021 COMPANY PUBLIC 456937 63 / 152 |
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