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CLRC66103HNT Datasheet(PDF) 25 Page - NXP Semiconductors |
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CLRC66103HNT Datasheet(HTML) 25 Page - NXP Semiconductors |
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25 / 152 page  NXP Semiconductors CLRC661 High performance NFC frontend CLRC661 plus 001aam305 Ack 0 (W) Ack 0 SA I2C slave address A7-A0 Frontend IC register address A6-A0 Ack DATA [7..0] SO SO [0..n] Ack 0 (W) Ack Optional, if the previous access was on the same register address Read Cycle Write Cycle 0 SA I2C slave address A7-A0 Frontend IC register address A6-A0 1 (R) Ack SA sent by master sent by slave I2C slave address A7-A0 Ack DATA [7..0] SO [0..n] 0..n Nack DATA [7..0] Figure 18. Register read and write access 8.4.4.9 I2CL-bus interface The CLRC661 provides an additional interface option for connection of a SAM. This logical interface fulfills the I2C specification, but the rise/fall timings will not be compliant to the I2C standard. The I2CL interface uses standard I/O pads, and the communication speed is limited to 5 MBaud. The protocol itself is equivalent to the fast mode protocol of I2C. The SCL levels are generated by the host in push/pull mode. The RC661 does not stretch the clock. During the high period of SCL, the status of the line is maintained by a bus keeper. The address is 01010xxb, where the last two bits of the address can be defined by the application. The definition of these bits can be done by two options. With a pin, where the higher bit is fixed to 0 or the configuration can be defined via EEPROM. Refer to the EEPROM configuration in Section 8.7. Parameter Min Max Unit fSCL 0 5 MHz tHD;STA 80 - ns tLOW 100 - ns tHIGH 100 - ns tSU;SDA 80 - ns tHD;DAT 0 50 ns tSU;DAT 0 20 ns tSU;STO 80 - ns tBUF 200 - ns Table 19. Timing parameter I2CL CLRC661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.7 — 23 June 2021 COMPANY PUBLIC 456937 25 / 152 |
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