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ICSSSTV32852YHT Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICSSSTV32852YHT Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 7 page  Integrated Circuit Systems, Inc. ICSSSTV32852 0513F—05/13/03 Recommended Application: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signals • Supports SSTL_2 class II specifications on inputs and outputs • Low-voltage operation - VDD = 2.3V to 2.7V • Available in 114 ball BGA package. DDR 24-Bit to 48-Bit Registered Buffer Truth Table 1 Block Diagram Notes: 1. H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care 2. Output level before the indicated steady state input conditions were established. CLK CLK# D1 VREF RESET# To 23 Other Channels Q1A Q1B CLK R D1 A B 123456 C D E F G H J K L M N P R T U V W Pin Configuration 114-Pin Ball BGA s t u p n Is t u p t u O Q # T E S E RK L C# K L CD Q L r o X g n i t a o l F r o X g n i t a o l F r o X g n i t a o l F L H ↑↓ HH H ↑↓ LL HH r o LH r o LX Q0 ) 2 ( Pin Configuration Assignments 1 234 5 6 A Q2A Q1A CLK CLK# Q1B Q2B B Q3A VDDQ GND GND VDDQ Q3B C Q5A Q4A VDDQ VDDQ Q4B Q5B D Q7A Q6A GND GND Q6B Q7B E Q8A GND VDDQ VDDQ GND Q8B F Q10A Q9A VDDQ VDDQ Q9B Q10B G Q12A Q11A GND GND Q11B Q12B H Q13A VDD VDDQ VDDQ VDD Q13B J Q14A Q15A GND GND Q15B Q14B K Q17A Q16A VDDQ VDDQ Q16B Q17B L Q18A Q19A GND GND Q19B Q18B M Q20A VDDQ GND GND VDDQ Q20B N Q22A Q21A VDDQ VDDQ Q21B Q22B P Q23A VDDQ GND GND VDDQ Q23B R Q24A VDD RESET# VREF VDD Q24B T D2 D1 D6 D18 D13 D14 U D4 D3 D10 D22 D15 D16 V D5 D7 D11 D23 D19 D17 W D8 D9 D12 D24 D21 D20 |
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