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TMS416400A Datasheet(PDF) 5 Page - Texas Instruments

Part No. TMS416400A
Description  4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS416400A Datasheet(HTML) 5 Page - Texas Instruments

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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by tRASP, the maximum RAS low time.
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge
of CAS latches the column addresses and enables the output. This feature allows the devices to operate at a
higher data bandwidth than conventional page-mode devices because data retrieval begins as soon as the
column address is valid rather than when CAS transitions low. This performance improvement is referred to as
enhanced-page mode. A valid column address can be presented immediately after row-address hold time has
been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max
(access time from CAS low) if tAA max (access time from column address) and tRAC have been satisfied. In the
event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle
is determined by the later occurrence of tCPA or tCAC.
address: A0 – A11 ( TMS416400A) and A0 – A10 (TMS417400A)
Twenty-two address bits are required to decode each of the 4 194 304 storage cell locations. For the
TMS416400A, 12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address
strobe (RAS). Ten column-address bits are set up on A0 through A9. For TMS417400A, 11 row-address bits
are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address bits are set up
on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar
to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip
select, activating the output buffers and latching the address bits into the column-address buffers.
write enable ( W )
The read- or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
data in (DQ1 – DQ4)
Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS with setup-and-hold times referenced to this signal. In a delayed-write- or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with the setup-and-hold time
referenced to this signal. Also, OE must be high to bring the output buffers to the high-impedance state prior
to impressing data on the I/O lines.
data out (DQ1 – DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after the access-time interval tCAC (which begins with
the negative transition of CAS) as long as tRAC and tAA are satisfied.


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