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PLL502-35OCL Datasheet(PDF) 1 Page - PhaseLink Corporation |
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PLL502-35OCL Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 9 page PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 1 FEATURES • Selectable 750kHz to 800MHz range. • Low phase noise output (@ 10kHz frequency offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for 155.52MHz, -115dBc/Hz for 622.08MHz). • CMOS (PLL502-37), PECL (PLL502-35 and PLL502-38) or LVDS (PLL502-39) output. • 12 to 25MHz crystal input. • No external load capacitor or varicap required. • Output Enable selector. • Wide pull range (+/-200 ppm) • Selectable 1/16 to 32x frequency multiplier. • 3.3V operation. • Available in 16-Pin (TSSOP or 3x3mm QFN). DESCRIPTION The PLL502-35 (PECL with inverted OE), PLL502-37 (CMOS), PLL502-38 (PECL), and PLL502-39 (LVDS) are high performance and low phase noise VCXO IC chips. They provide phase noise performance as low as –125dBc at 10kHz offset (at 155MHz), by multi- plying the input crystal frequency up to 32x. The wide pull range (+/- 200 ppm) and very low jitter make them ideal for a wide range of applications, including SONET/SDH and FEC. They accept fun- damental parallel resonant mode crystals from 12 to 25MHz. BLOCK DIAGRAM PIN CONFIGURATION (Top View) ^: Internal pull-up *: On 3x3 package, PLL502-35/-38 do not have SEL0 available: Pin 10 is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0 (pin 10), and pin11 is VDD. See pin assignment table for details. OUTPUT ENABLE LOGICAL LEVELS Part # OE State 0 (Default) Output enabled PLL502-38 1 Tri-state 0 Tri-state PLL502-35 PLL502-37 PLL502-39 1 (Default) Output enabled OE input: Logical states defined by PECL levels for PLL502-38 Logical states defined by CMOS levels for PLL502-37/-39 1 2 3 4 5 6 7 8 VDD 9 10 11 12 13 14 15 16 XIN XOUT SEL3^ SEL2^ OE VCON GND SEL0^ SEL1^ GND CLKC VDD CLKT GND GND P502-3x GND VDD CLKT CLKC 12 3 4 12 11 10 9 13 14 15 16 8 7 6 5 SEL3^ XOUT SEL2^ OE X+ X- OE Q PLL502-3x Vin Q PLL by-pass SEL PLL (Phase Locked Loop) Oscillator Amplifier w/ integrated varicaps |
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