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PLL502-35OC Datasheet(PDF) 6 Page - PhaseLink Corporation |
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PLL502-35OC Datasheet(HTML) 6 Page - PhaseLink Corporation |
6 / 9 page PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 6 8. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Differential Voltage VOD 247 355 454 mV VDD Magnitude Change ∆VOD -50 50 mV Output High Voltage VOH 1.4 1.6 V Output Low Voltage VOL 0.9 1.1 V Offset Voltage VOS 1.125 1.2 1.375 V Offset Magnitude Change ∆VOS RL = 100 Ω (see figure) 0 3 25 mV Power-off Leakage IOXD Vout = VDD or GND VDD = 0V ±1 ±10 uA Output Short Circuit Current IOSD -5.7 -8 mA 9. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf RL = 100 Ω CL = 10 pF (see figure) 0.2 0.7 1.0 ns OUT OUT V OD V OS 50 Ω 50 Ω OUT V DIFF R L = 100Ω C L = 10pF C L = 10pF LVDS Switching Test Circuit LVDS Levels Test Circuit LVDS Transistion Time Waveform OUT OUT OUT 0V (Differential) 0V 20% 80% 20% 80% t R t F V DIFF |
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