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PLL501-07SM Datasheet(PDF) 1 Page - PhaseLink Corporation |
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PLL501-07SM Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 6 page PLL501-05/-07 VCXO Clock Generator IC 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/10/01 Page 1 FEATURES • Integrated voltage-controlled crystal oscillator circuitry (VCXO) (pull range 200ppm minimum). • Ideal for ADSL (35.328MHz and 70.656MHz). • VCXO tuning range: 0 - 3.3V. • Integrated phase-locked loop (PLL) provides pullable output at 35.328MHz (for PLL501-05) and 70.656MHz (for PLL501-07) with a 13.248MHz low cost parallel resonant crystal. • Accepts fundamental-mode parallel resonant crystals from 8 to 15 MHz. • 3.3V supply voltage. • Small circuit board footprint (8-pin 0.150’’ SOIC). • 12mA output drives capability at TTL level. DESCRIPTIONS The PLL501-05 and PLL501-07 are monolithic low jitter, high performance CMOS VCXO chips. They allow the control of the output frequency with an input voltage (VIN), using a low cost crystal. The PLL501-05 and PLL501-07 are ideal for ADSL applications. With a low cost 13.248MHz crystal, the PLL501-05 provides a pullable 35.328MHz output clock, while the PLL501-07 provides a 70.656MHz output clock. PIN CONFIGURATION Table 1: Crystal / Output Frequencies DEVICE FXIN (MHz) CLK (MHz) PLL501-05 13.248 (8 to 15) 35.328 (2.667 x FXIN) PLL501-07 13.248 (8 to 15) 70.656 (5.333 x FXIN) Note: Contact PhaseLink for custom PLL Frequencies BLOCK DIAGRAM VIN XOUT XIN VCXO PLL CLK Output Buffer 1 2 3 4 5 6 7 8 XIN VDD VIN GND XOUT VDD CLK GND |
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